MODULE pld6 TITLE ' DSD v0.6 ' " " History: " " v0.5 Final breadboard version " v0.6 Corrected fc0, fc1 labels - First PCB version " " " Note: This is an ABEL v4 source file. " " Major functions: (1) catch bits C24 and C25. (2) encode fc0 from C24 " and C25. (3) digital audio routing " " Notes On Function: " " When bypass mode is selected (bypn=0), " daout = rxp = 4:1 mux output " When bypass mode is not selected (bypn=1), " rxp = 4:1 mux output " daout = txp " The 4:1 mux acts as a priority encoder. dain0 is highest priority. " " Hookup Diagram: " " In the following diagram, ---|>--- represents a driver or receiver. " " " +--------------+ +--------+ " | | | | " | | | | " | PAL | | CS8412 | " | | | | " | | | | " in 0 -----|>--------| dain0 rxp |-----| rxp | " in 1 -----|>--------| dain1 | | | " in 2 -----|>--------| dain2 | | | " in 3 -----|>--------| dain3 | | | " | | +--------+ " | | " +--------+ | | " | | | | " | CS8402 | | | " | | | | " | | | | " | txp |-----| txp daout |------+----|>--- out 0 " | | | | | " | | | | +----|>--- out 1 " +--------+ | | | " | | +----|>--- out 2 " | | | " | | +----|>--- out 3 " +--------------+ " " pld6 DEVICE 'p22V10'; " Inputs fsync pin 1; " clock cbl pin 2; csb pin 3; sel0n pin 4; " 0=select, 1=not select sel1n pin 5; sel2n pin 6; sel3n pin 7; bypn pin 8; " 0=bypass, 1=convert dain0 pin 9; " digital audio in from source deck dain1 pin 10; dain2 pin 11; dain3 pin 13; txp pin 14; " digital audio in from CS8402/txp " Outputs fc0,fc1 pin 23,22; n4,n3,n2,n1,n0 pin 21,20,19,18,17; daout pin 16 istype 'com'; " digital audio out to target deck rxp pin 15 istype 'com'; " digital audio out to CS8412/rxp reset,preset node 25,26; n = [n4,n3,n2,n1,n0]; c = .c.; x = .x.; equations reset = 0; preset = 0; fc0.oe = 1; fc1.oe = 1; n4.oe = 1; n3.oe = 1; n2.oe = 1; n1.oe = 1; n0.oe = 1; daout.oe = 1; rxp.oe = 1; txp.oe = 0; daout = (txp & bypn) # (dain0 & !sel0n & !bypn ) # (dain1 & sel0n & !sel1n & !bypn ) # (dain2 & sel0n & sel1n & !sel2n & !bypn ) # (dain3 & sel0n & sel1n & sel2n & !sel3n & !bypn ) # (dain0 & sel0n & sel1n & sel2n & sel3n & !bypn ); rxp = (dain0 & !sel0n ) # (dain1 & sel0n & !sel1n ) # (dain2 & sel0n & sel1n & !sel2n ) # (dain3 & sel0n & sel1n & sel2n & !sel3n ) # (dain0 & sel0n & sel1n & sel2n & sel3n ); n := (n + 1) & cbl; n := (31) & !cbl; fc1 := (csb & (n == 23)) # (fc1 & (n != 23)); " fc1 = c24 fc0 := (csb & !fc1 & (n == 24)) # (fc0 & (n != 24)); " notes: fc1 gets set before fc0 " fc1 = c24 " fc0 = c25 & !fc1 " multiple equations for n are OR'd by ABEL test_vectors ([fsync,cbl,csb] -> [ n,fc0,fc1]) " SET 1 [ c , 0 ,0 ] -> [31, x , x ]; " 1 startup [ c , 0 ,0 ] -> [31, x , x ]; " 2 [ c , 0 ,0 ] -> [31, x , x ]; " 3 [ c , 0 ,0 ] -> [31, x , x ]; " 4 [ c , 1 ,0 ] -> [ 0, x , x ]; " 5 normal operation [ c , 1 ,0 ] -> [ 1, x , x ]; " 6 [ c , 1 ,0 ] -> [ 2, x , x ]; " 7 [ c , 1 ,0 ] -> [ 3, x , x ]; " 8 [ c , 1 ,0 ] -> [ 4, x , x ]; " 9 [ c , 1 ,0 ] -> [ 5, x , x ]; " 10 [ c , 1 ,0 ] -> [ 6, x , x ]; " 11 [ c , 1 ,0 ] -> [ 7, x , x ]; " 12 [ c , 1 ,0 ] -> [ 8, x , x ]; " 13 [ c , 1 ,0 ] -> [ 9, x , x ]; " 14 [ c , 1 ,0 ] -> [10, x , x ]; " 15 [ c , 1 ,0 ] -> [11, x , x ]; " 16 [ c , 1 ,0 ] -> [12, x , x ]; " 17 [ c , 1 ,0 ] -> [13, x , x ]; " 18 [ c , 1 ,0 ] -> [14, x , x ]; " 19 [ c , 1 ,0 ] -> [15, x , x ]; " 20 [ c , 1 ,0 ] -> [16, x , x ]; " 21 [ c , 1 ,0 ] -> [17, x , x ]; " 22 [ c , 1 ,0 ] -> [18, x , x ]; " 23 [ c , 1 ,0 ] -> [19, x , x ]; " 24 [ c , 1 ,0 ] -> [20, x , x ]; " 25 [ c , 1 ,0 ] -> [21, x , x ]; " 26 [ c , 1 ,1 ] -> [22, x , x ]; " 27 [ c , 1 ,0 ] -> [23, x , x ]; " 28 [ c , 1 ,0 ] -> [24, x , 0 ]; " 29 fc1 becomes valid [ c , 1 ,1 ] -> [25, 1 , 0 ]; " 30 fc0 becomes valid [ c , 1 ,0 ] -> [26, 1 , 0 ]; " 31 latched [ c , 1 ,0 ] -> [27, 1 , 0 ]; " 32 [ c , 1 ,1 ] -> [28, 1 , 0 ]; " 33 [ c , 1 ,1 ] -> [29, 1 , 0 ]; " 34 [ c , 1 ,0 ] -> [30, 1 , 0 ]; " 35 [ c , 1 ,0 ] -> [31, 1 , 0 ]; " 36 [ c , 0 ,0 ] -> [31, 1 , 0 ]; " 37 [ c , 0 ,1 ] -> [31, 1 , 0 ]; " 38 [ c , 0 ,0 ] -> [31, 1 , 0 ]; " 39 [ c , 0 ,1 ] -> [31, 1 , 0 ]; " 40 " ([fsync,cbl,csb] -> [ n,fc0,fc1]) SET 2 [ c , 0 ,0 ] -> [31, 1 , 0 ]; " 1 startup [ c , 0 ,0 ] -> [31, 1 , 0 ]; " 2 [ c , 0 ,0 ] -> [31, 1 , 0 ]; " 3 [ c , 0 ,0 ] -> [31, 1 , 0 ]; " 4 [ c , 1 ,0 ] -> [ 0, 1 , 0 ]; " 5 normal operation [ c , 1 ,0 ] -> [ 1, 1 , 0 ]; " 6 [ c , 1 ,0 ] -> [ 2, 1 , 0 ]; " 7 [ c , 1 ,1 ] -> [ 3, 1 , 0 ]; " 8 [ c , 1 ,0 ] -> [ 4, 1 , 0 ]; " 9 [ c , 1 ,0 ] -> [ 5, 1 , 0 ]; " 10 [ c , 1 ,1 ] -> [ 6, 1 , 0 ]; " 11 [ c , 1 ,1 ] -> [ 7, 1 , 0 ]; " 12 [ c , 1 ,1 ] -> [ 8, 1 , 0 ]; " 13 [ c , 1 ,0 ] -> [ 9, 1 , 0 ]; " 14 [ c , 1 ,0 ] -> [10, 1 , 0 ]; " 15 [ c , 1 ,0 ] -> [11, 1 , 0 ]; " 16 [ c , 1 ,0 ] -> [12, 1 , 0 ]; " 17 [ c , 1 ,0 ] -> [13, 1 , 0 ]; " 18 [ c , 1 ,0 ] -> [14, 1 , 0 ]; " 19 [ c , 1 ,0 ] -> [15, 1 , 0 ]; " 20 [ c , 1 ,0 ] -> [16, 1 , 0 ]; " 21 [ c , 1 ,0 ] -> [17, 1 , 0 ]; " 22 [ c , 1 ,0 ] -> [18, 1 , 0 ]; " 23 [ c , 1 ,0 ] -> [19, 1 , 0 ]; " 24 [ c , 1 ,0 ] -> [20, 1 , 0 ]; " 25 [ c , 1 ,0 ] -> [21, 1 , 0 ]; " 26 [ c , 1 ,1 ] -> [22, 1 , 0 ]; " 27 [ c , 1 ,1 ] -> [23, 1 , 0 ]; " 28 [ c , 1 ,0 ] -> [24, 1 , 0 ]; " 29 fc1 becomes valid [ c , 1 ,0 ] -> [25, 0 , 0 ]; " 30 fc0 becomes valid [ c , 1 ,1 ] -> [26, 0 , 0 ]; " 31 latched [ c , 1 ,0 ] -> [27, 0 , 0 ]; " 32 [ c , 1 ,1 ] -> [28, 0 , 0 ]; " 33 [ c , 1 ,1 ] -> [29, 0 , 0 ]; " 34 [ c , 1 ,0 ] -> [30, 0 , 0 ]; " 35 [ c , 1 ,0 ] -> [31, 0 , 0 ]; " 36 [ c , 0 ,0 ] -> [31, 0 , 0 ]; " 37 [ c , 0 ,1 ] -> [31, 0 , 0 ]; " 38 [ c , 0 ,0 ] -> [31, 0 , 0 ]; " 39 [ c , 0 ,1 ] -> [31, 0 , 0 ]; " 40 " ([fsync,cbl,csb] -> [ n,fc0,fc1]) SET 3 [ c , 0 ,0 ] -> [31, 0 , 0 ]; " 1 startup [ c , 0 ,0 ] -> [31, 0 , 0 ]; " 2 [ c , 0 ,0 ] -> [31, 0 , 0 ]; " 3 [ c , 0 ,0 ] -> [31, 0 , 0 ]; " 4 [ c , 1 ,0 ] -> [ 0, 0 , 0 ]; " 5 normal operation [ c , 1 ,0 ] -> [ 1, 0 , 0 ]; " 6 [ c , 1 ,0 ] -> [ 2, 0 , 0 ]; " 7 [ c , 1 ,1 ] -> [ 3, 0 , 0 ]; " 8 [ c , 1 ,0 ] -> [ 4, 0 , 0 ]; " 9 [ c , 1 ,0 ] -> [ 5, 0 , 0 ]; " 10 [ c , 1 ,1 ] -> [ 6, 0 , 0 ]; " 11 [ c , 1 ,1 ] -> [ 7, 0 , 0 ]; " 12 [ c , 1 ,1 ] -> [ 8, 0 , 0 ]; " 13 [ c , 1 ,0 ] -> [ 9, 0 , 0 ]; " 14 [ c , 1 ,0 ] -> [10, 0 , 0 ]; " 15 [ c , 1 ,0 ] -> [11, 0 , 0 ]; " 16 [ c , 1 ,0 ] -> [12, 0 , 0 ]; " 17 [ c , 1 ,0 ] -> [13, 0 , 0 ]; " 18 [ c , 1 ,0 ] -> [14, 0 , 0 ]; " 19 [ c , 1 ,0 ] -> [15, 0 , 0 ]; " 20 [ c , 1 ,0 ] -> [16, 0 , 0 ]; " 21 [ c , 1 ,0 ] -> [17, 0 , 0 ]; " 22 [ c , 1 ,0 ] -> [18, 0 , 0 ]; " 23 [ c , 1 ,0 ] -> [19, 0 , 0 ]; " 24 [ c , 1 ,0 ] -> [20, 0 , 0 ]; " 25 [ c , 1 ,0 ] -> [21, 0 , 0 ]; " 26 [ c , 1 ,1 ] -> [22, 0 , 0 ]; " 27 [ c , 1 ,1 ] -> [23, 0 , 0 ]; " 28 [ c , 1 ,1 ] -> [24, 0 , 1 ]; " 29 fc1 becomes valid [ c , 1 ,0 ] -> [25, 0 , 1 ]; " 30 fc0 becomes valid [ c , 1 ,0 ] -> [26, 0 , 1 ]; " 31 latched [ c , 1 ,0 ] -> [27, 0 , 1 ]; " 32 [ c , 1 ,1 ] -> [28, 0 , 1 ]; " 33 [ c , 1 ,1 ] -> [29, 0 , 1 ]; " 34 [ c , 1 ,0 ] -> [30, 0 , 1 ]; " 35 [ c , 1 ,0 ] -> [31, 0 , 1 ]; " 36 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 37 [ c , 0 ,1 ] -> [31, 0 , 1 ]; " 38 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 39 [ c , 0 ,1 ] -> [31, 0 , 1 ]; " 40 " ([fsync,cbl,csb] -> [ n,fc0,fc1]) SET 4 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 1 startup [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 2 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 3 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 4 [ c , 1 ,0 ] -> [ 0, 0 , 1 ]; " 5 normal operation [ c , 1 ,0 ] -> [ 1, 0 , 1 ]; " 6 [ c , 1 ,0 ] -> [ 2, 0 , 1 ]; " 7 [ c , 1 ,1 ] -> [ 3, 0 , 1 ]; " 8 [ c , 1 ,0 ] -> [ 4, 0 , 1 ]; " 9 [ c , 1 ,0 ] -> [ 5, 0 , 1 ]; " 10 [ c , 1 ,1 ] -> [ 6, 0 , 1 ]; " 11 [ c , 1 ,1 ] -> [ 7, 0 , 1 ]; " 12 [ c , 1 ,1 ] -> [ 8, 0 , 1 ]; " 13 [ c , 1 ,0 ] -> [ 9, 0 , 1 ]; " 14 [ c , 1 ,0 ] -> [10, 0 , 1 ]; " 15 [ c , 1 ,0 ] -> [11, 0 , 1 ]; " 16 [ c , 1 ,0 ] -> [12, 0 , 1 ]; " 17 [ c , 1 ,0 ] -> [13, 0 , 1 ]; " 18 [ c , 1 ,0 ] -> [14, 0 , 1 ]; " 19 [ c , 1 ,0 ] -> [15, 0 , 1 ]; " 20 [ c , 1 ,0 ] -> [16, 0 , 1 ]; " 21 [ c , 1 ,0 ] -> [17, 0 , 1 ]; " 22 [ c , 1 ,0 ] -> [18, 0 , 1 ]; " 23 [ c , 1 ,0 ] -> [19, 0 , 1 ]; " 24 [ c , 1 ,0 ] -> [20, 0 , 1 ]; " 25 [ c , 1 ,0 ] -> [21, 0 , 1 ]; " 26 [ c , 1 ,1 ] -> [22, 0 , 1 ]; " 27 [ c , 1 ,1 ] -> [23, 0 , 1 ]; " 28 [ c , 1 ,1 ] -> [24, 0 , 1 ]; " 29 fc1 becomes valid [ c , 1 ,0 ] -> [25, 0 , 1 ]; " 30 fc0 becomes valid [ c , 1 ,0 ] -> [26, 0 , 1 ]; " 31 latched [ c , 1 ,0 ] -> [27, 0 , 1 ]; " 32 [ c , 1 ,1 ] -> [28, 0 , 1 ]; " 33 [ c , 1 ,1 ] -> [29, 0 , 1 ]; " 34 [ c , 1 ,0 ] -> [30, 0 , 1 ]; " 35 [ c , 1 ,0 ] -> [31, 0 , 1 ]; " 36 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 37 [ c , 0 ,1 ] -> [31, 0 , 1 ]; " 38 [ c , 0 ,0 ] -> [31, 0 , 1 ]; " 39 [ c , 0 ,1 ] -> [31, 0 , 1 ]; " 40 test_vectors ([fsync,dain0,dain1,dain2,dain3,txp ,sel0n,sel1n,sel2n,sel3n,bypn ] -> [rxp ,daout]) [ 0 , 0 , x , x , x , x , 0 , x , x , x , 0 ] -> [ 0 , 0 ]; " bypass [ 0 , 1 , x , x , x , x , 0 , x , x , x , 0 ] -> [ 1 , 1 ]; " [ 0 , x , 0 , x , x , x , 1 , 0 , x , x , 0 ] -> [ 0 , 0 ]; " [ 0 , x , 1 , x , x , x , 1 , 0 , x , x , 0 ] -> [ 1 , 1 ]; " [ 0 , x , x , 0 , x , x , 1 , 1 , 0 , x , 0 ] -> [ 0 , 0 ]; " [ 0 , x , x , 1 , x , x , 1 , 1 , 0 , x , 0 ] -> [ 1 , 1 ]; " [ 0 , x , x , x , 0 , x , 1 , 1 , 1 , 0 , 0 ] -> [ 0 , 0 ]; " [ 0 , x , x , x , 1 , x , 1 , 1 , 1 , 0 , 0 ] -> [ 1 , 1 ]; " [ 0 , 0 , x , x , x , x , 1 , 1 , 1 , 1 , 0 ] -> [ 0 , 0 ]; " no sel [ 0 , 1 , x , x , x , x , 1 , 1 , 1 , 1 , 0 ] -> [ 1 , 1 ]; " [ 0 , 0 , x , x , x , x , 0 , x , x , x , 1 ] -> [ 0 , x ]; " convert [ 0 , 1 , x , x , x , x , 0 , x , x , x , 1 ] -> [ 1 , x ]; " [ 0 , x , 0 , x , x , x , 1 , 0 , x , x , 1 ] -> [ 0 , x ]; " [ 0 , x , 1 , x , x , x , 1 , 0 , x , x , 1 ] -> [ 1 , x ]; " [ 0 , x , x , 0 , x , x , 1 , 1 , 0 , x , 1 ] -> [ 0 , x ]; " [ 0 , x , x , 1 , x , x , 1 , 1 , 0 , x , 1 ] -> [ 1 , x ]; " [ 0 , x , x , x , 0 , x , 1 , 1 , 1 , 0 , 1 ] -> [ 0 , x ]; " [ 0 , x , x , x , 1 , x , 1 , 1 , 1 , 0 , 1 ] -> [ 1 , x ]; " [ 0 , 0 , x , x , x , x , 1 , 1 , 1 , 1 , 1 ] -> [ 0 , x ]; " no sel [ 0 , 1 , x , x , x , x , 1 , 1 , 1 , 1 , 1 ] -> [ 1 , x ]; " [ 0 , x , x , x , x , 0 , x , x , x , x , 1 ] -> [ x , 0 ]; " 2:1 mux [ 0 , x , x , x , x , 1 , x , x , x , x , 1 ] -> [ x , 1 ]; " end pld6