(C) 2002, G. Forrest Cook
This circuit allows a remote microprocessor to be reset by a controlling host when the host sends a break signal over an RS-232 or RS-422 serial line. The break signal differs from a normal RS-232 character, it is a long-duration space (logic 0) signal that typically causes a framing error to be detected on the remote UART (serial to parallel) circuit. The break reset circuit detects the break signal and pulls the target microprocessor's reset line low for the duration of the signal.
If the remote machine resets into an EPROM-based serial monitor/loader program, it is possible for the host to restart the remote machine into the monitor program, load new code into the target machine's RAM and jump into the loaded program. The monitor/loader program only needs to have two functions: load a binary or hex file into an area of RAM and jump to the beginning of the program in the RAM.
Modern microprocessors such as an Arduino use EEPROM-based software loaders to achieve similar results. Other systems may use JTAG interfaces for loading new software.
The circuit is usually used for developing code on a target microprocessor, but it can also be used for applications where the target program lives on the host system. This system was once used to load code into a microprocessor-based satellite receiving system in Hawaii from a host system in Colorado using an Internet-based remote serial communications program.
A program loader for the Z-80 CPU is available below. The circuit has also been used with the Motorola 68HC11 EVB and the 6811 BUFFALO monitor program. See my Linux Cross Assemblers page for more info.
The circuit detects long duration zero-level signals (breaks) on the TTL serial data line. Note that the bi-polar RS-232 signals are inverted from the serial TTL signal so the RS-232 line is normally negative and goes positive during the break signal. On the TTL side, normal serial characters spend a short time pulsing to the zero state, these are ignored by the break reset circuit. Break signals hold the line low for several hundreds of milliseconds or longer, the circuit detects this and pulls the microprocessor reset line low for the duration of the break signal.
The 1N4148 diode on the left side of the schematic charges the 2.2uF capacitor from the normally-high logic level on the input. Low input signals slowly pull the charge on the 2.2uF capacitor down through the 10K resistor. High input signals quickly recharge the capacitor through the 1N4148 diode. A break signal lasts long enough to discharge the 2.2uF capacitor to the point where the following scmidt trigger gate changes state.
The 1N4148 on the right side of the schematic prevents the outputs from the two parallel 74HC14 gates from being shorted to ground by manual reset switches which are often found on target systems.
This circuit could be built using many different gate configurations. The 74HC14 was chosen because it is a common jelly bean part. The schmidt trigger snap-action is used to make a clean square wave on the output of the delay circuitry. The parallel inverters are optional if you need the two extra gates for other circuitry. Another option would be to use just two schmidt trigger gates and invert the logic by reversing the left 1N4148 diode and moving the 2.2uF capacitor between +5V and the diode/resistor junction.
The sbld.mac code is a Z-80 assembly language program that functions as a bootstrap loader for use with this Microprocessor RS-232 Reset circuit. The code runs on an ancient SD systems SBC200 Z-80 circuit board and can be made to work with other Z-80 boards by changing the initialization and serial port functions.
Back to FC's Computer Boot Management Circuits page.